One of the major problems involved in manufacturing semiconductor integrated circuits is achieving layer-to-layer registration of successive patterns required to form a working circuit. Typically, ten to fourteen layers must be registered in an overall working chip. In order to achieve the required registration it is common practice to place fiducial marks on the wafer. These fiducial marks can be detected by either light or electrons and serve as reference points from which to adjust the geometry of pattern exposure for registering the pattern of one wafer with the pattern of another. Fast and accurate registration requires a good signal-to-noise ratio during fiducial mark detection; however, since semiconductor wafers are coated with "resist" material prior to exposure of the circuit pattern, the fiducial mark must be read through the resist material with consequent loss of signal and degraded signal-to-noise ratios. This problem becomes more acute as the pattern feature sizes become smaller for two reasons: (1) since the features are smaller, registration must be more accurate; and (2) the resist material may become thicker since multiple layers of different materials are required in order to improve the resolution of the exposure and subsequent processing steps. Therefore, it would be desirable to have a simple method of removing the resist material from the area directly over the fiducial mark in order to maximize the signal when reading the fiducial mark position.
The most obvious way of clearing fiducial marks would be to introduce an additional conventional exposure and development step in the process. However, this approach only works with positive-acting resist material and would invariably introduce defects and reduce the yield of the final chips. Hence, there is clearly a need for a very low defect lithographic process to be used specifically for clearing fiducial marks.